It has long been appreciated that continuity of service can be maintained if a backup processor or system can be substituted for a degrading active processor or system. Examples may be found in air defense system (SAGE), command and control (SAC), astronautics (APOLLO), and airline reservation systems (SABRE). Such systems employed multiple processors operating in tandem on the same data such that, if an active system failed, its backup could replace it. Alternatively, by having multiple processors operating in tandem, it might be possible for an operator to pick and choose either which processor could be treated as the active controlling processor, or whether the results arrived at were credible. Such systems rarely concern themselves with maintaining the integrity of transactions caught in the middle when a backup processor replaces an active degrading processor. For example, in the airline reservation system, it was the responsibility of the ticket agent to confirm the status of any transactions in process and initiate any recovery procedures, and not that of the system itself.
Other pertinent prior art includes Doblmaier et al, U.S. Pat. No. 3,623,008, "Program-controlled Data Processing System", issued Nov. 23, 1971; Downing et al, U.S. Pat. No. 3,651,480, "Program Controlled Data Processing System", issued Mar. 21, 1972; and Griscom et al, U.S. Pat. No. 4,455,601, "Cross Checking Among Service Processors in a Multiprocessor System", issued Jun. 19, 1984.
Doblmaier and Downing describe fault tolerance in a telephone switching system having active and backup processors for controlling telephone connection traffic. In their system, denominated electronic switching system (ESS), each processor's components such as memory or control arrangements are switchably interconnectable therebetween. This means that a faulty memory in the active processor may be replaced immediately by its counterpart from a backup processor. This requires that a near-identical information state by maintained among the components of both processors in order to minimize loss of either calls in progress or calls being processed affected by this switchover.